Intel PXA26X - Manual (Page 279)

Intel® PXA26x Processor Family Developer’s Manual 7-11
Liquid Crystal Display Controller
7.4 Liquid Crystal Display External Palette and Frame
Buffers
The LCD controller supports a variety of user-programmable options, including display type and
size, frame buffer location, encoded pixel size, and output data width. Although all programmable
combinations are possible, the displays available on the market dictate which combinations of
these programmable options are practical. The processor external system memory limits the
throughput of the LCD controller’s DMAC, which, in turn, limits the size and type of display that
can be controlled. You must also determine the maximum bandwidth of the processor external bus
that the LCD controller is allowed to use without negatively affecting all other functions that the
processor must perform.
7.4.1 External-Palette Buffer
The external palette buffer is an off-chip memory area containing up to 256 16-bit entries to be
loaded into the internal palette RAM. The palette buffer data does not have to be at the beginning
of the external frame buffer, it can also be in a separate memory location. Palette data is 8 bytes (4
entries) for 1- and 2-bit pixels (the last 2 entries are loaded but not used with 1-bit pixels), 32 bytes
(16 entries) for 4-bit pixels, and 512 bytes (256 entries) for 8-bit pixels. The palette RAM is not
used and must not be loaded when using 16-bits per pixel.
After enabling the LCD controller, you must first load the palette RAM before processing any
frame data. After the initial load, the palette can be reloaded optionally on a frame-by-frame basis.
This is done when the color selection changes frame to frame. The palette RAM is always loaded
with DMA channel 0.
Figure 7-5 shows the format of the palette entries in little endian. Endian does not imply
endianness with respect to bytes and half-words within memory. It refers strictly to the ordering of
the palette entries; for example, whether palette entry 0 is at the MSB or the LSB of a word
boundary. The ordering of RGB values within the 16-bit entry is fixed for little endian. In
Figure 7-5 , base is the palette buffer base programmed in register FSADR.