Intel PXA26X - Manual (Page 589)

Intel® PXA26x Processor Family Developer’s Manual 17-5
Hardware UART
17.4.1 Reset
The UART is disabled on reset. To enable the UART, software must program the GPIO registers
(see
Section 4.1, “General-Purpose Input/Output” ) then set IER[UUE]. When the UART is
enabled, the receiver waits for a frame start bit and the transmitter sends data if it is available in the
Transmit Holding Register. Transmit data can be written to the Transmit Holding Register before
the UART unit is enabled. In FIFO mode, data is transmitted from the FIFO to the Transmit
Holding Register before it goes to the pin.
When the UART unit is disabled, the transmitter or receiver finishes the current byte and stops
transmitting or receiving more data. Data in the FIFO is not cleared and transmission resumes
when the UART is enabled.
17.4.2 FIFO Operation
The UART has a transmit FIFO and a receive FIFO each holding 64 characters of data. There are
three separate methods for moving data into/out of the FIFOs: interrupts, polling, and DMA.
17.4.2.1 FIFO Interrupt Mode Operation
17.4.2.1.1 Receive Interrupt
For a receive interrupt to occur, the receive FIFO and receive interrupts must be enabled. The
Interrupt Identification Register (IIR) bits 1 and 2 (IIR[IID]) change to show that receive data is
available when the FIFO reaches its trigger threshold. IIR[IID] changes to show the next waiting
interrupt when the FIFO drops below the trigger threshold. A change in IIR[IID] triggers an
interrupt to the core. Software reads IIR[IID] to determine the cause of the interrupt.
The receiver line status interrupt (IIR = 0xC6) has the highest priority and the received data
available interrupt (IIR = 0xC4) is lower. The line status interrupt occurs only when the character at
the front of the FIFO has errors.
The data ready bit (DR in the Line Status Register) is set when a character is transferred from the
shift register to the receive FIFO. The DR bit is cleared when the FIFO is empty.
17.4.2.1.2 Character Timeout Interrupt
A character timeout interrupt occurs when the receive FIFO and receive timeout interrupt are
enabled and all of the following conditions exist:
• At least one character is in the FIFO.
• The most recently received character was received more than four continuous character times
ago. If two stop bits are programmed, the second is included in this interval.
• The most recent FIFO read was performed more than four continuous character times ago.
After the processor reads one character from the receive FIFO or a new start bit is received, the
timeout interrupt is cleared and the timeout is reset. If a timeout interrupt has not occurred, the
timeout is reset when a new character is received or the processor reads the receive FIFO.