Intel PXA26X - Manual (Page 337)

Intel® PXA26x Processor Family Developer’s Manual 8-19
Synchronous Serial Port Controller
8.7.4.7 Transmit FIFO Level
The 4-bit Transmit FIFO Level bit indicates the number of entries currently in the transmit FIFO.
8.7.4.8 Receive FIFO Level
The 4-bit receive FIFO Level bit indicates the one less than number of entries in the receive FIFO.
8.7.5 SSP Register Address Map
Table 8-7 shows the SSP registers associated with the SSP and their physical addresses.
Table 8-7. SSP Register Address Map
Address Mnemonic Full Name
0x4100 0000 SSCR0 SSP Control Register 0
0x4100 0004 SSCR1 SSP Control Register 1
0x4100 0008 SSSR SSP Status Register
0x4100 000C — Reserved
0x4100 0010 SSDR (Write / Read) SSP Data Write Register/SSP Data Read Register