12 mmc_i_reg register, Section 15.5.12, “mmc_i_reg register – Intel PXA26X User Manual
Page 542
15-30
Intel® PXA26x Processor Family Developer’s Manual
MultiMediaCard Controller
15.5.12
MMC_I_REG Register
The MMC_I_REG register shows the currently requested interrupt. The FIFO request interrupts,
TXFIFO_WR_REQ, and RXFIFO_RD_REQ are masked off with the MMC_DMA_EN bit in the
MMC_CMDAT register. The software is responsible for monitoring these bits in program I/O
mode. The bits are cleared as described in
3
STOP_CMD
READY FOR STOP TRANSACTION COMMAND:
0 – Not masked
1 – Masked
2
END_CMD_
RES
END COMMAND RESPONSE:
0 – Not masked
1 – Masked
1
PRG_DONE
PROGRAMMING DONE:
0 – Not masked
1 – Masked
0
DATA_TRAN_
DONE
DATA TRANSFER DONE:
0 – Not masked
1 – Masked
Table 15-16. MMC_I_MASK Register
Physical Address
4110_0028
MMC_I_MASK Register
MMC
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
eser
ved
TXFIFO
_WR
_
R
E
Q
RX
F
IF
O
_
RD_
R
E
Q
CL
K
_
IS
_
O
F
F
ST
O
P
_
C
M
D
E
N
D
_
CM
D_
R
E
S
P
R
G
_
DO
NE
DA
T
A
_
T
RA
N_
DO
N
E
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Bits
Name
Description