Intel PXA26X - Manual (Page 79)

Intel® PXA26x Processor Family Developer’s Manual 3-13
Clocks and Power Manager
3. Perform a frequency change sequence to 33MHz mode. The CCCR value for this mode is
0x13F
4. Enter idle mode by selecting the PWRMODE[M] bit (refer to Section 3.7.2 )
3.4.7.2 Behavior in 33-MHz Idle Mode
In 33-MHz idle mode the CPU clocks are stopped. While in 33-MHz idle mode these features of
the processor all operate normally: the RTC timer, the OS timers including the watchdog timer, and
the GPIO interrupt capabilities.
When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is
set, only unmasked interrupts cause wake-up.
Enabled interrupts are interrupts that are allowed at the unit level. Masked interrupts are interrupts
that are prevented from interrupting the core based on the Interrupt Controller Mask Register
(ICMR).
3.4.7.3 Exiting 33-MHz Idle Mode
The 33-MHz idle mode exit procedure is the same as the exit procedure for normal idle mode.
However, because the I and F bits are set in the CPSR, the processor does not immediately jump to
the interrupt vector. Instead processing continues with the instruction following the last executed
instruction before 33-MHz idle mode was entered. If execution occurs from SDRAM, steps 1 and 2
must have been previously loaded into the instruction cache. The steps below are then taken:
1. Perform a frequency change to a supported run mode frequency, greater or equal to 100 MHz.
2. Take the SDRAM out of self refresh.
3. Clear the I and F bits in the CPSR. Execution immediately jumps to the pending interrupt
handler.
3.4.8 Frequency Change Sequence
Use the frequency change sequence to change the processor clock frequency. During the frequency
change sequence, the CPU, memory controller, LCD controller, and DMA clocks stop. The other
peripheral units continue to function during the frequency change sequence. Use this mode to
change the frequency from the default condition at initial boot-up. It may also be used as a power-
saving feature that lets the processor run at the minimum required frequency when the software
requires major changes in frequency.
3.4.8.1 Preparing for the Frequency Change Sequence
Software must complete these steps before it initiates the frequency change sequence:
1. Configure the memory controller to ensure SDRAM contents are maintained during the
frequency change sequence. The memory controller’s refresh timer must be programmed to
match the maximum refresh time associated with the slower of two frequencies (current and
desired). The SDRAM divide by two must be set to a value that prevents the SDRAM
frequency from exceeding the specified frequency. For example, to change from 100/100 to
133/66, the SDRAM bus must be set to divide by two before the frequency change. To change
from 133/66 to 100/100, the SDRAM must be set to one-to-one after the frequency change
sequence is completed. See
Section 6, “Memory Controller” for more details.