2 transmit holding register (thr), Table 10-4. transmit holding register - thr, 3 divisor latch registers (dll and dlh) – Intel PXA26X User Manual
Page 373
Intel® PXA26x Processor Family Developer’s Manual
10-7
Universal Asynchronous Receiver/Transmitter
10.4.2.2
Transmit Holding Register (THR)
In non-FIFO mode, the THR holds the data byte that is to be transmitted next. When the TSR is
emptied, the contents of the THR are loaded in the TSR and the LSR[TDRQ] is set to a 1.
In FIFO mode, a write to the THR puts data into the top of the FIFO. The data at the front of the
FIFO is loaded to the TSR when that register is empty.
10.4.2.3
Divisor Latch Registers (DLL and DLH)
Each UART contains a programmable baud rate generator that can take the 14.7456-MHz-fixed-
input clock and divide it by 1 to (2
16
–1). For the FFUART and the STUART, the divisor is from 4
to 2
16
–1. The baud rate generator output frequency is 16 times the baud rate. Two 8-bit latches
store the divisor in a 16-bit binary format. Load these divisor latches during initialization to ensure
that the baud rate generator operates properly. If each divisor latch is loaded with a 0, the 16X
clock stops. The divisor latches are accessed with a word write.
The baud rate of the data shifted in to or out of a UART is given by the formula:
For example: if the divisor is 24, the baud rate is 38400 bps.
The divisor’s reset value is 0x0002.
Table 10-4. Transmit Holding Register
–
THR
Base (DLAB=0)
Transmit Holding Register
UART
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
eser
ved
TH
R
7
TH
R
6
TH
R
5
TH
R
4
TH
R
3
TH
R
2
TH
R
1
TH
R
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write only
Bits
Name
Description
31:8
—
Reserved
7:0
THR[7:0]
TRANSMIT HOLDING REGISTER BITS 7 – 0:
Data byte transmitted least significant bit first.
BaudRate
14.7456 MHz
16xDivisor
(
)
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