Table 15-15. mmc_prtbuf register, 11 mmc_i_mask register, Table 15-16. mmc_i_mask register – Intel PXA26X User Manual
Page 541: Section 15.5.11, “mmc_i_mask register, Table 15-15 on
Intel® PXA26x Processor Family Developer’s Manual
15-29
MultiMediaCard Controller
15.5.11
MMC_I_MASK Register
The MMC_I_MASK register masks off the various interrupts when set to a 1 (see
Table 15-15. MMC_PRTBUF Register
Physical Address
4110_0024
MMC_PRTBUF Register
MMC
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
eser
ved
BU
F
_
P
A
R
T
_
F
UL
L
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
31:1
—
Reserved
0
BUF_PART_
FULL
BUFFER PARTIALLY FULL:
0 – Buffer is not partially full.
1 – Buffer is partially full and must be swapped to the other transmit buffer
Software must clear this bit before sending the next command.
Table 15-16. MMC_I_MASK Register
Physical Address
4110_0028
MMC_I_MASK Register
MMC
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
R
eser
ved
TXFIFO
_WR
_
R
E
Q
RXF
IF
O
_
R
D_
R
E
Q
CL
K
_
IS
_
O
F
F
STO
P
_
C
M
D
EN
D_
C
M
D_
RE
S
P
R
G
_
DO
NE
DA
T
A
_
T
R
A
N
_
DO
NE
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Bits
Name
Description
31:7
—
Reserved
6
TXFIFO_WR_
REQ
TRANSMIT FIFO WRITE REQUEST:
0 – Not masked
1 – Masked
5
RXFIFO_RD_
REQ
RECEIVE FIFO READ REQUEST:
0 – Not masked
1 – Masked
4
CLK_IS_
OFF
CLOCK IS OFF:
0 – Not masked
1 – Masked