Intel PXA26X - Manual (Page 622)

18-6 Intel® PXA26x Processor Family Developer’s Manual
Internal Flash
strh r9, [r8] ;/* No need for cache alignment since second flash chip */
ldrh r9, [r8] ;/* Read identifier second bus cycle, address=0x0 */
cmp r9, #0x89 ;/* Intel manufacturer code */
bne EndSynchronousMode
;//--- Write to second 128 Mbit flash. Registers are already configured, just need
to change the
;//--- address in r4 to point to second flash
orr r4, r4, #0x01000000
strh r5, [r4] ;/* Have to do 16 bit writes to 16 bit wide flash */
strh r6, [r4] ;/* Entering synch mode automatically places flash in read
array mode */
b EndSynchronousMode
align 0x20
aligned_address_32
str r5, [r4] ;/* Have to do 32 bit writes to 32 bit wide flash */
str r6, [r4] ;/* Entering synch mode automatically places flash in read
array mode */
str r7, [r3] ;/* Write SXCNFG value */
b %F1 ;/* Delay the prefetcher enough for SXCNFG to be written */
1
EndSynchronousMode
18.2 Additional Intel StrataFlash® Memory Information
Additional information on Intel StrataFlash® memory can be found on developer.intel.com at http:/
/developer.intel.com/design/flcomp/prodbref/298398.htm.