7 single block read, Set mmc_i_mask to 0x1e, Wait for the mmc_i_reg[data_tran_done] interrupt – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
MultiMediaCard Controller
5. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has
finished programming. Software may wait for MMC_I_REG[PRG_DONE] or start another
command sequence on a different card.
6. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
To address a different card, the software sends a select command to that card by sending a basic no
data command and response transaction. To address the same card, the software must wait for
MMC_I_REG[PRG_DONE] interrupt. This ensures that the card is not in the busy state.
15.4.7
Single Block Read
In a single block read command, the software must stop the clock and set the registers as described
in section
Section 15.4.4, “No Data Command and Response Sequence”
The following registers must be set before the clock is started:
•
Update the following bits in the MMC_CMDAT register:
— Set the MMC_CMDAT[RESPONSE_FORMAT] bit.
— Set the MMC_CMDAT[DATA_EN] bit.
— Clear the MMC_CMDAT[WRITE/READ] bit.
— Clear the MMC_CMDAT[STREAM_BLOCK] bit.
— Clear the MMC_CMDAT[BUSY] bit.
— Clear the MMC_CMDAT[INIT] bit.
•
Set MMC_NOB register to 0x0001.
•
Set MMC_BLKLEN register to the number of bytes per block.
•
Turn the clock on.
After it turns the clock on, the software must perform the following steps:
1. Wait for the response as described in section
Section 15.4.4, “No Data Command and
2. Read data from the MMC_RXFIFO FIFO, as data becomes available in the FIFO, and
continue reading until all data is read from the FIFO.
3. Set MMC_I_MASK to 0x1e.
4. Wait for the MMC_I_REG[DATA_TRAN_DONE] interrupt.
5. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
15.4.8
Multiple Block Write
The multiple block write mode is similar to the single block write mode, except that multiple
blocks of data are transferred. Each block is the same length. All the registers are set as they are for
the single block write, except that the MMC_NOB register is set to the number of blocks to be
written.