Intel PXA26X - Manual (Page 590)

17-6 Intel® PXA26x Processor Family Developer’s Manual
Hardware UART
17.4.2.1.3 Transmit Interrupt
Transmit interrupts can only occur when the transmit FIFO and transmit interrupt are enabled. The
transmit data request interrupt occurs when the transmit FIFO is at least half empty. The interrupt is
cleared when the THR is written or the IIR is read.
17.4.2.2 FIFO Polled Mode Operation
When the FIFOs are enabled, clearing both IER[DMAE] and IER[4:0] places the serial port in
FIFO polled operating mode. The receiver and the transmitter are controlled separately. Either one
or both can be in polled mode. In polled mode, software checks receiver and transmitter status via
the LSR. The processor polls the following bits for receive and transmit data service:
• Receive Data Service – The processor checks the LSR[DR] (data ready) bit which is set when
one or more bytes remain in the receive FIFO or Receive Buffer Register (RBR).
• Transmit Data Service – The processor checks the LSR[TDRQ] (transmit data request) bit
which is set when transmitter needs data.
The processor can also check the LSR[TEMT] (transmitter empty) bit, which is set when the
transmit FIFO and Holding register are empty.
17.4.2.3 FIFO DMA Mode Operation
The UART has two DMA requests: One for transmit data service, and one for receive data service.
DMA requests are generated in FIFO mode only. The requests are activated by setting
IER[DMAE].
• Data Transmit Data Service – When IER[DMAE] is set, if the transmit FIFO is less than half
full, the transmit-DMA request is generated. The DMA controller then writes data to the FIFO.
For each DMA request, the DMA controller can send 8, 16, or 32 bytes of data to the FIFO.
The actual number of bytes to be transmitted is programmed in the DMA controller.
• Data Receive Data Service – When IER[DMAE] is set, the receive-DMA request is
generated when the receive FIFO reaches its trigger threshold with no errors in its entries. The
DMA controller then reads data from the FIFO. For each DMA request, the DMA controller
can read 8, 16, or 32 bytes of data from the FIFO. The actual number of bytes to be read is
programmed in the DMA controller along with the bus width.
17.4.2.4 DMA Receive Programming Errors
If the DMA channel stops prematurely due to the end of a descriptor chain or other error, the
processor must be notified, since the DMA controller can no longer service the UARTs FIFOs. If
this occurs, the processor must correct the situation by programming another descriptor or by
servicing the FIFOs via interrupt or polling modes as described previously. The DMA must
interrupt on the event of a stopped channel by setting DCSR[StopIrqEn].
17.4.2.5 DMA Error Handling
An error interrupt is used when DMA requests are enabled. The interrupt is generated when LSR
bit 7 is set to 1. This happens when a receive DMA request is not generated and the receive FIFO
has an error. The error interrupt tells the processor to handle the data in the receive FIFO through
programmed I/O. The error interrupt is enabled when DMA requests are enabled and cannot be
masked. Receiver line status interrupts occur when the error is at the front of the FIFO.