Zilog Z80180 User Manual
Family mpu, Z8018x, User manual
Table of contents
Document Outline
- Family MPU
- Manual Objectives
- Table of Contents
- List of Figures
- List of Tables
- Z80180, Z8S180, Z8L180 MPU Operation
- Features
- General Description
- Pin Description
- Architecture
- Operation Modes
- CPU Timing
- Wait State Generator
- HALT and Low Power Operation Modes (Z80180-Class Processors Only)
- Low Power Modes (Z8S180/Z8L180 only)
- Add-On Features
- STANDBY Mode
- STANDBY Mode Exit with BUS REQUEST
- STANDBY Mode EXit with External Interrupts
- IDLE Mode
- STANDBY-QUICK RECOVERY Mode
- Internal I/O Registers
- MMU Register Description
- Interrupts
- Interrupt Acknowledge Cycle Timings
- Interrupt Sources During RESET
- Dynamic RAM Refresh Control
- DMA Controller (DMAC)
- Asynchronous Serial Communication Interface (ASCI)
- Baud Rate Generator (Z8S180/Z8L180-Class Processors Only)
- Clocked Serial I/O Port (CSI/O)
- CSI/O Registers Description
- Programmable Reload Timer (PRT)
- Miscellaneous
- Software Architecture
- DC Characteristics
- AC Characteristics
- Timing Diagrams
- Instruction Set
- Instruction Summary
- Op Code Map
- Bus Control Signal Conditions
- Operating Modes Summary
- Status Signals
- I/O Registers