Zilog Z80180 User Manual
Page 155
Z8018x
Family MPU User Manual
140
UM005003-0703
Figure 54. RTS0 Timing Diagram
Figure 55 illustrates the ASCI interrupt request generation circuit.
Figure 55. ASCI Interrupt Request Circuit Diagram
T1
T1
T2
T3
WR
RTS0 Flag
RTS0 Pin
Phi
I/O Instruction
I/O write cycle
IEF1
ASCI0 Interrupt
Request
ASCI1 Interrupt
Request
TIE1
TDRE1
RIE1
RDRF1
OVRN1
PE1
FE1
TIE0
TDRE0
RIE0
DCD0
OVRN0
PE0
FE0
RDRF0