Zilog Z80180 - Manual (Page 61)

Z8018x
Family MPU User Manual
46
UM005003-0703
DMA DMA Source Address Register Ch 0L SAR0L XX100000 20H 93
DMA Source Address Register Ch 0H SAR0H XX100001 21H 93
DMA Source Address Register Ch 0B SAR0B XX100010 22H 93
DMA Destination Address Register Ch
0L DAR0L XX100011 23H 94
DMA Destination Address Register Ch
0H DAR0H XX100100 24H 94
DMA Destination Address Register Ch
0B DAR0B XX100101 25H 94
DMA Byte Count Register Ch 0L BCR0L XX100110 26H 94
DMA Byte Count Register Ch 0H BCR0H XX100111 27H 94
DMA Memory Address Register Ch 1L MAR1L XX101000 28H 94
DMA Memory Address Register Ch 1H MAR1H XX101001 29H 94
DMA Memory Address Register Ch 1B MAR1B XX101010 2AH 94
DMA I/0 Address Register Ch 1L IAR1L XX101011 2BH 102
DMA I/0 Address Register Ch 1H IAR1H XX101100 2CH 102
Reserved XX101101 2DH
DMA Byte Count Register Ch 1L BCR1L XX101110 2EH 94
DMA Byte Count Register Ch 1H BCR1H XX101111 2FH 94
DMA Status Register DSTAT XX110000 30H 95
DMA Mode Register DMODE XX110001 31H 97
DMA/WAIT Control Register DCNTL XX110010 32H 101
Table 6. I/O Address Map for Z80180-Class Processors Only (Continued)
Register Mnemonic
Address
Binary Hex Page