Zilog Z80180 - Manual (Page 321)

Z8018x
Family MPU User Manual
UM005003-0703
305
A
AC characteristics 197
Address generation, physical 64
Address map
I/O 44
I/O address translation 57
Logical examples 55
Logical memory organization 58
Logical space configuration 59
Physical address transition 56
Addressing
Extended 182
I/O 184
Indexed 182
Indirect 181
Architecture 12
ASCI
Baud rate selection 142
Block diagram 117
Clock diagram 141
Control register A0 125
Control register A1 128
Control register B 131
Functions 116
Interrupt request circuit diagram 140
Register descriptions 117
Status register 0 120
Status register 1 123
Asynchronous serial communications interface
(ASCI)
14
B
Baud rate selection
ASCI 142
CSI/O 150
Block diagram 6
ASCI 117
CSI/O 146
DMAC 92
MMU 56
PRT 157
Bus state controller 13
C
Central processing unit (CPU) 14
Circuit diagram, ASCI interrupt request 140
Clock generator 13
Clocked serial I/O (CSI/O) 14
CPU register configurations 176
CPU timing
Basic instruction 23
BUSREQ/BUSACK Bus Exchange 25
HALT and Low Power modes 31
I/O data read/write 22
Internal I/O registers 41
MMU register description 60
Op Code fetch timing 18
Operand and data read/write 20
RESET 25
Wait state generator 27