Zilog Z80180 User Manual
Page 274
Z8018x
Family MPU User Manual
258
UM005003-0703
INC (IX+ d)
INC (IY+d)
DEC (IX+d)
DEC (IY+d)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
T1T2T3 1st operand
Address
d
0
1
0
1
1
1
1
MC4~M
C5
TiTi *
Z
1
1
1
1
1
1
1
MC6
T1T2T3 X+ d
IY+ d
DATA
0
1
0
1
1
1
1
MC7
T1
*
Z
1
1
1
1
1
1
1
MC8
T1T2T3 IX+ d
IY+d
DATA
1
0
0
1
1
1
1
INC ww
DEC ww
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
Ti
*
Z
1
1
t
1
1
1
1
INC IX
INC IY
DEC IX
DEC IY
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
Ti
*
Z
1
1
1
1
1
1
1
IN A,(m)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 1st operand
Address
m
0
1
0
1
1
1
1
MC3
T1T2T3 m to A0~A7
A to A8~A15
DATA
0
1
1
0
1
1
1
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle
States
Address
Data
RD WR MREQ
IORQ M1 HALT ST