Zilog Z80180 - Manual (Page 63)

Z8018x
Family MPU User Manual
48
UM005003-0703
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only)
Register Mnemonic
Address
Binary Hex Page
ASCI ASCI Control Register A Ch 0 CNTLA0 XX000000 00H 125
ASCI Control Register A Ch 1 CNTLA1 XX000001 01H 128
ASCI Control Register B Ch 0 CNTLB0 XX000010 02H 132
ASCI Control Register B Ch 1 CNTLB1 XX000011 03H 132
ASCI Status Register Ch 0 STAT0 XX000100 04H 120
ASCI Status Register Ch 1 STAT1 XX000101 05H 123
ASCI Transmit Data Register Ch 0 TDR0 XX000110 06H 118
ASCI Transmit Data Register Ch 1 TDR1 XX000111 07H 118
ASCI Receive Data Register Ch 0 RDR0 XX001000 08H 119
ASCI Receive Data Register Ch 1 RDR1 XX001001 09H 119
ASCI0 Extension Control Register 0 ASEXT0 XX010010 12H 135
ASCI1 Extension Control Register 1 ASEXT1 XX010011 13H 136
ASCI0 Time Constant Low ASTC0L XX011010 1AH 137
ASCI0 Time Constant High ASTC0H XX001011 1BH 137
ASCI1 Time Constant Low ASCT1L XX001100 1CH 138
ASCI1 Time Constant High ASCT1H XX001101 1DH 138
CSI0 CSI0 Control Register CNTR XX001010 0AH 147
CSI0 Transmit/Receive Data Register TRD XX1011 0BH 149