Figure 84. dma control signals – Zilog Z80180 User Manual
Page 216
Z8018x
Family MPU User Manual
200
UM005003-0703
Figure 84. DMA Control Signals
47
45 46
48
18
(level sense)
DREQ1
(edge sense)
TENDi
ST
PHI
T
1
T
2
T
W
T
3
T
1
17
DREQ1
CPU or DMA Read/Write Cycle (Only DMA Write Cycle for TENDi)
45
46
*
**
CPU Cycle
Starts
DMA Cycle
Starts
Notes:
*T
DRQS
and T
DRQH
are specified for the rising edge of the clock followed by T
3
.
**T
DRQS
and T
DRQH
are specified for the rising edge of the clock.