Z8018x family mpu user manual – Zilog Z80180 User Manual
Page 293
Z8018x
Family MPU User Manual
UM005003-0703
277
SET b, (IX+d)
SET b, (IY+d)
RES b, (IX+d)
RES b, (IY+d)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
T1T2T3 1st operand
Address
d
0
1
0
1
1
1
1
MC4
T1T2T3 3rd Op Code
Address
3rd Op
Code
0
1
0
1
0
1
1
MC5
T1T2T3 IX+d
IY+d
DATA
0
1
0
1
1
1
1
MC6
Ti
*
Z
1
1
1
1
1
1
1
MC7
T1T2T3 IX+ d
IY+d
DATA
1
0
0
1
1
1
1
SLP**
MC1
T1T2T3 1st Op Code
Address
1stOp
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
—
—
7FFFFH
Z
1
1
1
1
1
0
1
TSTIO m**
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
T1T2T3 1st operand
Address
m
0
1
0
1
1
1
1
MC4
T1T2T3 C to A0~A7
00H to
A8~A15
DATA
0
1
1
0
1
1
1
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle
States
Address
Data
RD WR MREQ
IORQ M1 HALT ST