Zilog Z80180 - Manual (Page 322)

Z8018x
Family MPU User Manual
UM005003-0703
306
CSI/O
Baud rate selection 150
Block diagram 146
Control/Status register 147, 150, 159,
160, 161, 172
External clock receivetiming diagram 156
External clock transmit timing diagram
154
Internal clock receivetiming diagram 155
Internal clock transmit timing diagram
153
interrupt request generation 151
Operation 151
Receive/Transmit timing diagram 204
Timer initialization, count down and reload
timing diagram 163
Timer output control 163
Timer output timing diagram 164
Cycle timing 87
D
Data formats 131
DC characteristics
Absolute maximum ratings 185
Z80180 186
Z8L180 189
Z8S180 187
DCD0 timing diagram 139
Description, general 1
Design rules, circuit board 170
Direct register bit field definitions 181
Divide ratio 134
DMA
Controller (DMAC) 90
CYCLE STEAL mode timing diagram
106
Edge-sense timing diagram 108
Interrupt request generation 114
Level-sense timing diagram 107
Mode register (DMODE) 97
Operation 104
Status register (DSTAT) 95
TEND0 output timing diagram 108
Transfer request 110
WAIT control register 100
DMAC
Block diagram 92
Register 93
DRAM refresh intervals 89
Dynamic RAM refresh control 86
E
E clock
BUS RELEASE, SLEEP and SYSTEM
STOP modes timing diagram 201
Memory and I/O R/W cycles timing dia-
gram 201
Minimum timing example of PWEL and
PWEH timing diagram 202
Timing conditions 166
Timing diagram (R/W and INTACK cy-