Zilog Z80180 - Manual (Page 144)

Z8018x
Family MPU User Manual
UM005003-0703
129
5 TE R/W Transmitter Enable — When TE is set to 1, the ASCI
transmitter is enabled. When TE is reset to 0, the
transmitter is disabled and any transmit operation in
progress is interrupted. However, the TDRE flag is not
reset and the previous contents of TDRE are held. TE is
cleared to 0 in IOSTOP mode, and during RESET.
4 CKA1D R/W CKA1 Clock Disable — When CKA1D is set to 1, the
multiplexed CKA1/
TEND0 pin is used for the TEND0
function. When CKA1 D is 0, the pin is used as CKA1, an
external data dock input/output for channel 1
3 MPBR/
EFR R/W Multiprocessor Bit Receive/Error Flag Reset — When
multiprocessor mode is enabled (MP in CNTLB is 1),
MPBR, when read, contains the value of the MPB bit for
the last receive operation. When written to 0, the EFR
function is selected to reset all error flags (OVRN, FE and
PE) to 0. MPBR/EFR is undefined during RESET.
Bit
Position Bit/Field R/W
Value Description