Zilog Z80180 - Manual (Page 214)

Z8018x
Family MPU User Manual
198
UM005003-0703
Memory Read/Write Cycle timing is the sam as I/O Read/Write Cycle
except there are no automatica Wait States (TW), and MREQ is active
instead of IORQ.
Figure 82. AC Timing Diagram 2
PHI
INT0,1,2
31
32
33
40
30
28
15
16
29
39
41 42
34
35 34
35
36 37
38 38
43 44
14
10
NMI
M1
IORQ
Data IN
MREQ
RFSH
BUSREQ
BUSACK
MREQ, RD
WR, IORQ
HALT
Output Buffer Off
A19–0, D7–0