Zilog Z80180 User Manual
Page 272
Z8018x
Family MPU User Manual
256
UM005003-0703
DJNZ j
(If Br
¹ 0)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
Ti*2
*
Z
1
1
1
1
1
1
1
MC3
T1T2T3 1st operand
Address
j-2
0
1
0
1
1
1
1
MC4~M
C5
TiTi
*
Z
1
1
1
1
1
1
1
DJNZ j
(If Br=0)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
Ti*1
*
Z
1
1
1
1
1
1
1
MC3
T1T2T3 1st operand
Address
j-2
0
1
0
1
1
1
1
EI*3
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
EX DE, HL
EXX
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
EX AF, AF’
MC1
T1T2T3 1st Op Code
Address
1st
Op Code
0
1
0
1
0
1
0
MC2
Ti
*
Z
1
1
1
1
1
1
1
EX (SP), HL
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 SP
DATA
0
1
0
1
1
1
1
MC3
T1T2T3 SP+1
DATA
0
1
0
1
1
1
1
MC4
Ti
*
Z
1
1
1
1
1
1
1
MC5
T1T2T3 SP+1
H
1
0
0
1
1
1
1
MC6
T1T2T3 SP
L
1
0
0
1
1
1
1
*2 DMA,REFRESH, or BUS RELEASE cannot be executed after this state. (Request is ignored)
*3 Interrupt request is not sampled.
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle
States
Address
Data
RD WR MREQ
IORQ M1 HALT ST