Figure 59. transmit timing diagram–internal clock – Zilog Z80180 User Manual
Page 168
Z8018x
Family MPU User Manual
UM005003-0703
153
CSI/O and RESET
During RESET each bit in the CNTR is initialized as defined in the
CNTR register description. CSI/O transmit and receive operations in
progress are aborted during RESET. However, the contents of TRDR are
not changed.
Figure 59. Transmit Timing Diagram–Internal Clock
CKS
TXS
TE
EF
LSB
MSB
Read or write of CSI/O
Transmit/Receive
Data Register