Zilog Z80180 User Manual
Page 312
Z8018x
Family MPU User Manual
296
UM005003-0703
ASCI Transmit Data
Register Channel 0:
ASCI Transmit Data
Register Channel 1:
ASCI Receive Data
Register Channel 0:
ASCI Receive Data
Register Channel 1:
CSI/O Control Register:
TDR0
TDR1
TSR0
TSR1
CNTR
0
6
0
7
0
8
0
9
0
A
Table 57. Internal I/O Registers (Continued)
Register
Mnemonics Address
Remarks
EF
EIE
TE
—
SS2
SS1
SS0
R
R/W
R/W
R/W
R/W
R/W
R/W
Receive Enable
End Interrupt Enable
End Flag
1
0
0
0
0
1
1
1
bit
during RESET
R/W
Speed Select
Transmit Enable
RE
SS2 1 0
0 0 0
0 0 1
0 1 0
0 1 1
Phi
¸
20
¸
¸
¸
40
160
80
External
Baud Rate
SS2 1 0
1 0 0
1 0 1
1 1 0
1 1 1
Phi
¸
320
¸
¸
640
1280
Baud Rate
frequency <
¸ 20)