Zilog Z80180 - Manual (Page 136)

Z8018x
Family MPU User Manual
UM005003-0703
121
5 PE R Parity Error — PE is set to 1 when a parity error is
detected on an incoming data byte and ASCI parity
detection is enabled (the MOD1 bit of CNTLA is set to
1). PE is cleared to 0 when the EFR bit (Error Flag Reset)
of CNTLA is written to 0, when DCD0 is High, in
IOSTOP mode, and during RESET.
4 FE R Framing Error — If a receive data byte frame is
delimited by an invalid stop bit (that is, 0, should be 1),
FE is set to 1. FE is cleared to 0 when the EFR bit (Error
Flag Reset) of CNTLA is written to 0, when DCD0 is
High, in IOSTOP mode, and during RESET.
3 RIE R/W Receive Interrupt Enable — RIE must be set to 1 to
enable ASCI receive interrupt requests. When RIE is 1, if
any of the flags RDRF, OVRN, PE, or FE become set to
1, an interrupt request is generated. For channel 0, an
interrupt is also generated by the transition of the external
DCD0 input from Low to High.
2 DCD0 R Data Carrier Detect — Channel 0 has an external
DCD0 input pin. The DCD0 bit is set to 1 when the
DCD 0 input is HIGH. It is cleared to 0 on the first read of
(STAT0, following the DCD0 input transition from
HIGH to LOW and during RESET. When DCD0 is 1,
receiver unit is reset and receiver operation is inhibited.
1 TDRE R Transmit Data Register Empty — TDRE = 1 indicates
that the TDR is empty and the next transmit data byte is
written to TDR. After the byte is written to TDR, TDRE
is cleared to 0 until the ASCI transfers the byte from TDR
to the TSR and then TDRE is again set to 1. TDRE is set
to 1 in IOSTOP mode and during RESET. When the
external
CTS input is High, TDRE is reset to 0.
Bit
Position Bit/Field R/W
Value Description