Zilog Z80180 - Manual (Page 135)

Z8018x
Family MPU User Manual
120
UM005003-0703
0
, data can be written into the ASCII Receive Data Register, and the data
can be read.
ASCI Status Register 0, 1 (STAT0, 1)
Each channel status register allows interrogation of ASCI
communication, error and modem control signal status, and enabling or
disabling of ASCI interrupts.
ASCI Status Register 0 (STAT0: 04H)
Bit 7 6 5 4 3 2 1 0
Bit/Field RDRF OVRN PE FE RIE DCD0 TDRE TIE
R/W R R R R R/W R R R/W
Reset 0 0 0 0 0 0 0 0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
Value Description
7 RDRF R Receive Data Register Full — RDRF is set to 1 when an
incoming data byte is loaded into RDR. If a framing or
parity error occurs, RDRF remains set and the receive
data (which generated the error) is still loaded into RDR.
RDRF is cleared to 0 by reading RDR, when the DCD0
input is High, in IOSTOP mode, and during RESET.
6 OVRN R Overrun Error — OVRN is set to 1 when RDR is full
and RSR becomes full. OVRN is cleared to 0 when the
EFR bit (Error Flag Reset) of CNTLA is written to 0,
when DCD0 is High, in IOSTOP mode, and during
RESET.