Zilog Z80180 User Manual
Page 294
Z8018x
Family MPU User Manual
278
UM005003-0703
TST g**
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
Ti
*
Z
1
1
1
1
1
1
1
TST m**
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
T1T2T3 1st operand
Address
m
0
1
0
1
1
1
1
TST (HL)**
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
2
0
2
0
2
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
Ti
*
Z
1
1
1
1
1
1
1
MC4
T1T23
HL
Data
0
1
0
1
1
1
1
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle
States
Address
Data
RD WR MREQ
IORQ M1 HALT ST