Zilog Z80180 - Manual (Page 158)

Z8018x
Family MPU User Manual
UM005003-0703
143
Baud Rate Generator
(Z8S180/Z8L180-Class Processors Only)
The Z8S180/Z8L180 Baud Rate Generator (BRG) features two modes.
The first is the same as in the Z80180. The second is a 16-bit down
counter that divides the processor clock by the value in a 16-bit time
constant register, and is identical to the DMSCC BRG. This feature allows
1 f ¸ 30
0 16
0 0 0 ¸1 f ¸ 480 9600 f ¸ 30
0 0 1 2 960 4800 60
0 1 0 4 1920 2400 120
0 1 1 8 3840 1200 0 240
1 0 0 16 7680 600 480
1 0 1 32 15360 300 960
1 1 0 64 30720 150 1920
1 1 1 — fc ¸ 16 — — — I fc
1 64
0 0 0 ¸1 f ¸ 1920 2400 f ¸ 30
0 0 1 2 3840 1200 60
0 1 0 4 7680 600 120
0 1 1 8 15360 300 0 240
1 0 0 16 30720 150 480
1 0 1 32 61440 75 960
1 1 0 64 122880 37.5 1920
1 1 1 — fc ¸ 64 — — — I fc
Table 19. ASCI Baud Rate Selection (Continued)
Prescaler
Sampling
Rate Baud Rate
General
Divide
Ratio
Baud Rate (Example)
(BPS) CKA
PS
Divide
Ratio
DR Rate
SS2 SS1 SS0 Divide
Ratio
f = 6.144
MHz f = 4.608
MHz f = 3.072
MHz
I/O
Clock
Frequency