Zilog Z80180 User Manual
Page 150
Z8018x
Family MPU User Manual
UM005003-0703
135
ASCI0 Extension Control Register (I/O Address: 12H) (Z8S180/L180-Class Processors
Only)
Bit
7
6
5
4
3
2
1
0
Bit/Field
RDRF
Int
Inhibit
DCD0
Disable
CTS0
Disable
X1 Bit
Clk
ASCI0
BRG0
Mode
Break
Feature
Enable
Break
Detect
(RO)
Send
Break
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field
R/W
Value Description
7
RDRF
Interrupt
Inhibit
R/W
0
1
RDRF Interrupt Inhibit On
RDRF Interrupt Inhibit Off
6
DCD0
Disable
R/W
0
1
DCD0 Auto-enables Rx
DCD0 advisory to SW
5
CTS0
Disable
R/W
0
1
CTS0 Auto-enable Tx
CTS0 advisory to SW
4
X1 Bit
Clk
ASCI0
R/W
0
1
CKA0 /16 or /64
CKA0 is bit clock
3
BRG0
Mode
R/W
0
1
As S180
Enable 16-bit BRG counter
2
Break
Feature
Enable
R/W
0
1
Break Feature Enable On
Break Feature Enable Off
1
Break
Detect
(RO)
R/W
0
1
Break Detect On
Break Detect Off