Z8018x family mpu user manual – Zilog Z80180 User Manual
Page 271
Z8018x
Family MPU User Manual
UM005003-0703
255
CPI
CPD
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
T1T2T3 HL
DATA
0
1
0
1
1
1
1
MC4
~MC6
TiTiTi
*
Z
1
1
1
1
1
1
1
CPIR
CPDR
(If BC
R
¹ 0 and
Ar = (HL)
M
)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
T1T2T3 HL
DATA
0
1
0
1
1
1
1
MC4~M
C8
TiTiTi
TiTi
*
Z
1
1
1
1
1
1
1
CPIR
CPDR
(If BC
R
=0 or
Ar=(HL)
M
)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
T1T2T3 HL
DATA
0
1
0
1
1
1
1
MC4~M
C6
TiTiTi
*
Z
1
1
1
1
1
1
1
CPL
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
DAA
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
Ti
*
Z
1
1
1
1
1
1
1
DI*1
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
* 1 Interrupt request is not sampled.
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle
States
Address
Data
RD WR MREQ
IORQ M1 HALT ST