Zilog Z80180 - Manual (Page 64)

Z8018x
Family MPU User Manual
UM005003-0703
49
Timer Data Register Ch 0 L TMDR0L XX001100 0CH 159
Data Register Ch 0 H TMDR0H XX001101 0DH 159
Reload Register Ch 0 L RLDR0L XX001110 0EH 159
Reload Register Ch 0 H RLDR0H XX001111 0FH 159
Timer Control Register TCR XX010000 10H 161
Reserved XX010001 11H
Data Register Ch 1 L TMDR1L XX010100 14H 160
Data Register Ch 1 H TMDR1H XX010101 15H 160
Reload Register Ch 1 L RLDR1L XX010110 16H 160
Reload Register Ch 1 H RLDR1H XX010111 17H 160
Others Free Running Counter
Reserved
FRC XX011000 18H 172
XX011001 19H
XX011111 1DH
Clock Multiplier Register CMR XX011110 1EH 52
CPU Control Register CCR XX011111 1FH 53
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued)
Register Mnemonic
Address
Binary Hex Page