Zilog Z80180 - Manual (Page 90)

Z8018x
Family MPU User Manual
UM005003-0703
75
Figure 35. NMI Timing
INT0 - Maskable Interrupt Level 0
The next highest priority external interrupt after NMI is INT0. INT0 is
sampled at the falling edge of the clock state prior to T3 or T1 in the last
machine cycle. If INT0 is asserted LOW at the falling edge of the clock
state prior to T3 or T1 in the last machine cycle, INT0 is accepted. The
interrupt is masked if either the IEF1 flag or the ITEO (Interrupt Enable
0) bit in ITC are reset to
0
. After RESET the state is as follows:
1. IEF1 is
0
, so INT0 is masked
2. ITE0 is
1
, so INT0 is enabled by execution of the El (Enable
Interrupts) instruction
The INT0 interrupt is unique in that 3 programmable interrupt response
modes are available - Mode 0, Mode 1 and Mode 2. The specific mode is
selected with the IM 0, IM 1 and IM 2 (Set Interrupt Mode) instructions.
During RESET, the Z8X180 is initialized to use Mode 0 for INT0. The 3
interrupt response modes for INT0 are:
•
Mode 0–Instruction fetch from data bus
•
Mode 1–Restart at logical address
0038H
•
Mode 2–Low-byte vector table address fetch from data bus
INT0 Mode 0
During the interrupt acknowledge cycle, an instruction is fetched from the
data bus (DO–D7) at the rising edge of T3. Often, this instruction is one
of the eight single byte RST (RESTART) instructions which stack the PC
and restart execution at a fixed logical address. However, multibyte
instructions can be processed if the interrupt acknowledging device can
provide a multibyte response. Unlike all other interrupts, the PC is not
automatically stacked: