Zilog Z80180 User Manual
Page 268
Z8018x
Family MPU User Manual
252
UM005003-0703
ADD A,g
ADC A,g
SUB g
SBC A,g
AND g
OR g
XOR g
CP g
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
Ti
*
Z
1
1
1
1
1
1
1
ADD A,m
ADC A,m
SUB m
SBC A,m
AND m
OR m
XOR m
CP m
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 1st operand
Address
m
0
1
0
1
1
1
1
ADD A, (HL)
ADC A, (HL)
SUB (HL)
SBC A, (HL)
AND HU
OR (HL)
XOR (HL)
CP (HL)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 HL
DATA
0
1
0
1
1
1
1
ADD A, (IX+ d)
ADD A, (IY+d)
ADC A, (IX+d)
ADC A, (IY+d)
SUB (lX+d)
SUB (IY+d)
SBC A, (IX+ d)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
SBC A, (IY+ d)
AND (IX+d)
MC3
T1T2T3 1st operand
Address
d
0
1
0
1
1
1
1
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle
States
Address
Data
RD WR MREQ
IORQ M1 HALT ST