Z8018x family mpu user manual – Zilog Z80180 User Manual
Page 287
Z8018x
Family MPU User Manual
UM005003-0703
271
OTIMR**
OTDMR**
(if Br= 0)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
Ti
*
Z
1
1
1
1
1
1
1
MC4
T1T2T3 HL
DATA
0
1
0
1
1
1
1
MC5
T1T2T3 C to A0~A7
00H to
A8~A15
DATA
1
0
1
0
1
1
1
MC6
Ti
*
Z
1
1
1
1
1
1
1
OUTI
OUTD
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
T1T2T3 HL
DATA
0
1
0
1
1
1
1
MC4
T1T2T3 BC
DATA
1
0
1
0
1
1
1
OTIR
OTDR
(If Br`
¹ 0)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
T1T2T3 HL
DATA
0
1
0
1
1
1
1
MC4
T1T2T3 BC
DATA
1
0
1
0
1
1
1
MC5~M
C6
TiTi
*
Z
1
1
1
1
1
1
1
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle
States
Address
Data
RD WR MREQ
IORQ M1 HALT ST