Zilog Z80180 User Manual
Page 120
Z8018x
Family MPU User Manual
UM005003-0703
105
In addition, the operation of channel 0 DMA with the on-chip ASCI
(Asynchronous Serial Communication Interface) as well as Channel 1
DMA are described.
Memory to Memory—Channel 0
For memory to/from memory transfers, the external DREQ0 input is not
used for DMA transfer timing. Rather, the DMA operation is timed in one
of two programmable modes – BURST or CYCLE STEAL. In both
modes, the DMA operation automatically proceeds until termination
(shown by byte count-BCR0) =
0
.
In BURST mode, the DMA operation proceeds until termination. In this
case, the CPU cannot perform any program execution until the DMA
operation is completed. In CYCLE STEAL mode, the DMA and CPU
operation are alternated after each DMA byte transfer until the DMA is
completed. The sequence:
•
1 CPU Machine Cycle
•
DMA Byte Transfer
is repeated until DMA is completed. Figure 46 describes CYCLE STEAL
mode DMA timing.