Zilog Z80180 - Manual (Page 311)

Z8018x
Family MPU User Manual
UM005003-0703
295
ASCI Status Channel 0: STAT0 0 4
ASCI Status Channel 1: STAT1 0 5
Table 57. Internal I/O Registers (Continued)
Register Mnemonics Address Remarks
R R R R R/W R R R/W
Transmit Interrupt Enable
0 0 0 0 * ** 0
RDRF OVRN PE DCD0 TDRE TIE FE
invalid
bit
during RESET
R/W
RIE
Transmit Data Register Empty
Data Carrier Detect
Receive Interrupt Enable
Framing Error
Parity Error
Overrun Error
Receive Data Register Full
TDRE
L
H
1
0
** CTS 0 Pin
* DCD 0 : Depending on the condition of DCD 0 Pin.
R R R R R/W R R R/W
Transmit Interrupt Enable
0 0 0 0 0 1 0
RDRF OVRN PE CTS1E TDRE TIE FE
0
bit
during RESET
R/W
RIE
Transmit Data Register Empty
CTS1 Enable
Receive Interrupt Enable
Framing Error
Parity Error
Overrun Error
Receive Data Register Full