Zilog Z80180 - Manual (Page 30)

Z8018x
Family MPU User Manual
UM005003-0703
15
OPERATION MODES
The Z8X180 can be configured to operate like the Hitachi HD64180. This
functionality is accomplished by allowing user control over the M1,
IORQ, WR, and RD signals. The Operation Mode Control Register
(OMCR), illustrated in Figure 5, determines the M1 options, the timing of
the IORQ, RD, and WR signals, and the RETI operation.
Figure 5. Operation Mode Control Register
M1E (M1 Enable): This bit controls the M1 output and is set to a
1
during
RESET.
When M1E is
1
, the M1 output is asserted Low during the Op Code fetch
cycle, the INT0 acknowledge cycle, and the first machine cycle of the
NMI acknowledge. This action also causes the M1 signal to be Active
during both fetches of the RETI instruction sequence, and may cause
corruption of the external interrupt daisy chain. Therefore, this bit must be
0
for the Z8X180. When M1E is
0
the M1 output is normally inactive and
asserted Low only during the refetch of the RETI instruction sequence
and the INT0 acknowledge cycle (Figure 6).
Operation Mode Control Register
Bit 7 6 5 4 0
Bit/Field M1E M1TE IOC Reserved
R/W R/W W R/W –
Reset 1 1 1 –
Note: R = Read W = Write X = Indeterminate? = Not Applicable