Zilog Z80180 User Manual
Page 292
Z8018x
Family MPU User Manual
276
UM005003-0703
RST v
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
~MC3
TiTi
*
Z
1
1
1
1
1
1
1
MC4
T1T2T3 SP-1
PCH
1
0
0
1
1
1
1
MC5
T1T2T3 SP-2
PCL
1
0
0
1
1
1
1
SCF
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
SET b,g
RES b,g
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
Ti
*
Z
1
1
1
1
1
1
1
SET b. (HL)
RES b, (HL)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
MC2
T1T2T3 2nd Op Code
Address
2ndOp
Code
0
1
0
1
0
1
1
MC3
T1T2T3 HL
DATA
0
1
0
1
1
1
1
MC4
Ti
*
Z
1
1
1
1
1
1
1
MC5
T1T2T3 HL
DATA
1
0
0
1
1
1
1
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle
States
Address
Data
RD WR MREQ
IORQ M1 HALT ST