Zilog Z80180 - Manual (Page 231)

Z8018x
Family MPU User Manual
UM005003-0703
215
SUBC SBC A,g 10 011 g S D 1 4 Ar-gr-c ®Ar ­ ­ ­ V S ­
SBC A,(HL) 10 011 110 S D 1 6 Ar-(HL)
M
-c ®Ar ­ ­ ­ V S ­
SBC A,m 11 011 110 S D 2 6 Ar-m-c ®Ar ­ ­ ­ V S ­
SBC A,(IX + d) 11 011 101 S D 3 14 Ar-(IX + d)
M
-c ®Ar ­ ­ ­ V S ­
10 011 110
SBC A,(IY + d) 11 111 101 S D 3 14 Ar-(IY + d)
M
-c ®Ar ­ ­ ­ V S ­
10 011 110
TEST TST g** 11 101 101 S 2 7 Ar ·gr ­ ­ S P R R
00 g 100
TST {HL)** 11101101 S 2 10 Ar ·(HL)
M
­ ­ S P R R
00 110 100
TST m** 11 101 101 S 3 9 Ar ·m ­ ­ S P R R
01 100 100
XOR XOR g 10 101 g S D 1 4 Ar Å + gr ®Ar ­ ­ R P R R
XOR (HL) 10 101 110 S D 1 6 Ar Å + (HL)
M
®Ar ­ ­ R P R R
XOR m 11 101 110 S D 2 6 Ar Å + m ®Ar ­ ­ R P R R
XOR (IX + d) 11 011 101 S D 3 14 Ar Å + (IX + d) )
M
®Ar ­ ­ R P R R
10 101 110
Table 38. Arithmetic and Logical Instructions (8-bit) (Continued)
Operation
Name
Mnemonics Op Code
Addressing
Bytes States Operation
Flags
7 6 4 2 1 0
Immed Ext Ind Reg RegI Imp Rel S Z H P/V N C