Zilog Z80180 User Manual
Page 318
Z8018x
Family MPU User Manual
302
UM005003-0703
Interrupt Vector Low
Register
INT/TRAP Control
Register
Refresh Control Register:
IL
ITC
RCR
3
3
3
4
3
6
Table 57. Internal I/O Registers (Continued)
Register
Mnemonics Address
Remarks
R/W
R/W
R/W
0
0
0
0
0
0
0
IL7
IL6
IL5
—
—
—
—
0
bit
during RESET
R/W
—
Interrupt Vector Low
R/W
R
R/W
0
0
1
1
0
0
0
TRAP
UF0
—
—
1
bit
during RESET
R/W
—
Unidentified Fetch Object
ITE2
ITE1
ITE0
R/W
R/W
INT Enable 2,1,0
TRAP
R/W
R/W
1
1
1
1
1
0
0
REFE
REFW
—
—
1
bit
during RESET
R/W
—
Refresh Wait State
CYC1
CYC0
R/W
R/W
Cycle select
Refresh Enable
—
0 0
10 states
20
0 1
1 0
1 1
Interval of Refresh Cycle
40
80