Zilog Z80180 User Manual
Page 290
Z8018x
Family MPU User Manual
274
UM005003-0703
RETI (Z)
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0*5
1
1
0
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0*5
1
1
1
MC3
~MC5
TiTiTi
*
Z
1
1
1
1
1*5
1
1
1
MC6
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0*5
0
1
1
MC7
Ti
*
Z
1
1
1
1
1*5
1
1
1
MC8
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0*5
0
1
1
MC9
T1T2T3 SP
data
0
1
0
1
1*5
1
1
1
MC10
T1T2T3 SP+1
data
0
1
0
1
1*5
1
1
1
RLCA
RLA
RRCA
RRA
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
RLC g
RL g
MC1
T1T2T3 1st Op Code
Address
1st Op
Code
0
1
0
1
0
1
0
RRC g
RR g
SLA g
SRA g
SRL g
MC2
T1T2T3 2nd Op Code
Address
2nd Op
Code
0
1
0
1
0
1
1
MC3
Ti
*
Z
1
1
1
1
1
1
1
*5 The upper and lower data show the state of M1 when IOC = 1 and IOC = 0 respectively.
Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)
Instruction
Machine
Cycle
States
Address
Data
RD WR MREQ
IORQ M1 HALT ST