Z8018x
Family MPU User Manual
197
UM005003-0703
Timing Diagrams
Figure 81. AC Timing Diagram 1
PHI
ADDRESS
WAIT
MREQ
IORQ
RD
WR
M1
ST
Data IN
Data OUT
RESET
11
67
68
62
63
68
67
62
63
15
16
17
10
14
9
22
13
11
28
7
29
7
8
20
19
19
20
11
12
6
9
13
25
11
Opcode Fetch Cycle
T
1
1
2
3
4
5
15
16
21
27
18
I/O Write Cycle*
I/O Read Cycle*
T
2
T
W
T
3
T
1
T
2
T
W
T
3
T
1
23
24
26
