Zilog Z80180 User Manual
Page 79
Z8018x
Family MPU User Manual
64
UM005003-0703
Figure 29. Physical Address Generation
Figure 30. Physical Address Generation 2
Adder
Comparator
D3 — D0
D7 — D4
0
12 11
15
8
4
4
4
MMU Common/
Bank Area
Register
MMU Common/
Register
Bank Area
MMU Common Base Reg.
MMU Bank Base Reg.
0 0 0 0 0 0 0 0
4
8
Logical
Address
(64K)
Physical
(512 k or 1 M)
(19) 18
12 11
0
Address
Logical
Address
(64 k)
11
12
15
(7)
4 3
0
(19)
18
16 15
12 11
Base Register
(8 bit)
Physical
Address
0
0
(1 M)