Zilog Z80180 - Manual (Page 66)

Z8018x
Family MPU User Manual
UM005003-0703
51
INT IL Register (Interrupt Vector Low
Register) IL XX110011 33H 67
INT/TRAP Control Register ITC XX110100 34H 68
Reserved XX110101 35H
Refresh Refresh Control Register RCR XX110110 36H 88
Reserved XX110111 37H
MMU MMU Common Base Register CBR XX111000 38H 61
MMU Bank Base Register BBR XX111001 39H 62
MMU Common/Bank Area Register CBAR XX111010 3AH 60
I/O Reserved XX111011 3BH
XX111101 3DH
Operation Mode Control Register OMCR XX111110 3EH 15
I/O Control Register ICR XX111111 3FH 42
Table 7. I/O Address Map (Z8S180/Z8L180-Class Processors Only) (Continued)
Register Mnemonic
Address
Binary Hex Page