Zilog Z80180 - Manual (Page 60)

Z8018x
Family MPU User Manual
UM005003-0703
45
Timer Data Register Ch 0 L TMDR0L XX001100 0CH 159
Data Register Ch 0 H TMDR0H XX001101 0DH 159
Reload Register Ch 0 L RLDR0L XX001110 0EH 159
Reload Register Ch 0 H RLDR0H XX001111 0FH 159
Timer Control Register TCR XX010000 10H 161
Reserved XX010001 11H
XX010011 13H
Data Register Ch 1 L TMDR1L XX010100 14H 160
Data Register Ch 1 H TMDR1H XX010101 15H 160
Reload Register Ch 1 L RLDR1L XX010110 16H 159
Reload Register Ch 1 H RLDR1H XX010111 17H 159
Others Free Running Counter
Reserved
FRC XX011000 18H 172
XX011001 19H
XX011111 1FH
Table 6. I/O Address Map for Z80180-Class Processors Only (Continued)
Register Mnemonic
Address
Binary Hex Page