Zilog Z80180 User Manual
Page 69
Z8018x
Family MPU User Manual
54
UM005003-0703
Memory Management Unit (MMU)
The Z8X180 features an on-chip MMU which performs the translation of
the CPU 64KB (16-bit addresses
0000H
to
FFFFH
) logical memory
address space into a 1024KB (20-bit addresses
00000H
to
FFFFFH
)
physical memory address space. Address translation occurs internally in
parallel with other CPU operation.
Logical Address Spaces
The 64KB CPU logical address space is interpreted by the MMU as
consisting of up to three separate logical address areas, Common Area 0,
Bank Area, and Common Area 1.
As depicted in Figure 23, a variety of logical memory configurations are
possible. The boundaries between the Common and Bank Areas can be
programmed with 4KB resolution.
2
LNIO
R/W
0
1
Standard Drive
33% Drive on certain external I/O
1
LNCPUCTL
R/W
0
1
Standard Drive
33% Drive on CPU control signals
0
LNAD/
DATA
R/W
0
1
Standard Drive
33% drive on A10–A0, D7–D0
Bit
Position Bit/Field
R/W
Value Description