Dynamic ram refresh control – Zilog Z80180 User Manual
Page 101
Z8018x
Family MPU User Manual
86
UM005003-0703
Figure 43. INT1, INT2 and Internal Interrupts Timing Diagram
Dynamic RAM Refresh Control
The Z8X180 incorporates a dynamic RAM refresh control circuit
including 8-bit refresh address generation and programmable refresh
timing. This circuit generates asynchronous refresh cycles inserted at the
programmable interval independent of CPU program execution. For
systems which do not use dynamic RAM, the refresh function can be
disabled.
When the internal refresh controller determines that a refresh cycle should
occur, the current instruction is interrupted at the first breakpoint between
machine cycles. The refresh cycle is inserted by placing the refresh
address on A0–A7 and the RFSH output is driven Low.
T1
T1
T1
T1
T1
T1
T2
T2
T2
T2
T2
TW*
T3
T3
T3
T3
T3
T3
T2
TW*
Ti
PC Stacking
Vector Table Read
Op Code
fetch cycle
INT1, INT2, internal interrupt acknowledge cycle
Last MC
INT1,2
A0
–
A19
M1
MREQ
IORQ
RD
WR
PC
SP-1
SP-2
Vector
Vector+1
Starting
Address
Starting
Starting
* Two Wait States are automatically inserted.
D0
–
D7
ST
MC: Machine Cycle
PCL
PCH
Phi
address (L)
address (H)