Zilog Z80180 - Manual (Page 325)

Z8018x
Family MPU User Manual
UM005003-0703
309
CSI/O control/status 147, 150, 159,
160, 161, 172
Direct bit field definitions 181
DMA mode (DMODE) 97
DMA status 95
DMA/WAIT control 100
Flag 178
I/O Control 42
I/O control (ICR) 42
Indirect addressing 181
INT/TRAP control (ITC) 67
Interrupt Vector (I) 66
MMU bank base (BBR) 62
MMU common bank area (CBAR) 60
MMU common base (CBR) 61
Operation mode control 15, 84
PRT timer control register 161
Refresh control 88
Relative addressing
Addressing
Relative 183
RETI
control signal states 85
Instruction sequence 84
RTS0 timing diagram 140
S
Secondary bus interface 165
SLEEP mode 33
SLP execution cycle timing diagram
Timing diagram
SLP execution cycle 203
Status summary table 10
SYSTEM STOP mode 35
T
Test conditions, standard 205
Timer initialization, count down and reload
163
Timer output timing diagram
Timing diagram
Timer output 202
Timing diagram 163
AC 197
Bus Exchange Timing During CPU Inter-
nal Operation 27
Bus Exchange Timing During Memory
Read 26
CPU (I/O Read/Write cycles) 199
CSI/O external clock receive 156
CSI/O external clock transmit 154
CSI/O internal clock receive 155
CSI/O internal clock transmit 153
CSI/O receive/transmit 204
CSI/O timer output 164
DCD0 139
DMA control signals 200
DMA CYCLE STEAL mode 106
DMA edge-sense 108
DMA level-sense 107