Zilog Z80180 - Manual (Page 323)

Z8018x
Family MPU User Manual
UM005003-0703
307
cles) 167
Timing diagram (SLEEP and SYSTEM
STOP modes) 168
Extended addressing 182
External clock rise and fall time 204
F
Features 1
H
HALT mode 31
I
I/O
Addressing 184
Control register (ICR) 42
I/O control register 42
Immediate addressing
Addressing
Immediate 183
Indexed addressing 182
Indirect addressing 181
Input ris and fall time (except EXTAL and RE-
SET) timing diagram
204
Instruction set
CPU registers 175
Flag register 178
Summary 173
INT0
Interrupt mode 2 timing 80
Mode 1 interrupt sequence 77
Mode 1 timing 78
INT0 mode 0 timing 76
Interrupt
Acknowledge cycle timings 82
Control registers and flags 65
Controller 13
CSI/O request generation 151
DMA request generation 114
Enable (ITE) 68
INT/TRAP control register (ITC) 67
Maskable interrupt 0 (INT0) 75
Non-maskable 72
PRT request generation 164
Sources 65
Sources during reset 83
TRAP 70
Vector register (I) 66
IOSTOP mode 35
L
Level-sense programming 109
Logical memory organization 58
M
M1 temporary enable timing 16
Maskable interrupt level 0 75