Figure 36. int0 mode 0 timing diagram, Int0 mode 1, Both ief1 and ief2 flags are reset to – Zilog Z80180 User Manual
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Z8018x
Family MPU User Manual
76
UM005003-0703
The TRAP interrupt occurs if an invalid instruction is fetched
during Mode 0 interrupt acknowledge. (Reference Figure 36.)
Figure 36. INT0 Mode 0 Timing Diagram
INT0 Mode 1
When INT0 is received, the PC is stacked and instruction execution
restarts at logical address
0038H
. Both IEF1 and IEF2 flags are reset to
0
,
Note:
Phi
A0
–
A19
WR
RD
MREQ
D0
–
D7
M1
IORQ
T1
T3
Ti
Ti
TW
T2
T1
T2
T3
T1
T2
T3
TW
PC is pushed onto stack
RST instruction execution
INT0 acknowledge cycle
Last MC
PC
SP-1
SP-2
PCH
PCL
RST instruction
MC: Machine Cycle
*Two Wait States are automatically inserted
*
*
INT0